1. Field of the Invention
The present invention relates to a memory device having a bank architecture, and a sense amplifier control device used for the memory device.
2. Description of the Background Art
FIG. 36 is a circuit diagram of a background art RAM (DRAM or SDRAM). A memory array (mem-array) is meant to define a range of elements decoded by one column decoder and one row decoder. One bank corresponds to one memory array. One bank BANK100 is illustrated in FIG. 36 as decoded by one row decoder RD and one column decoder CD.
An architecture for controlling a plurality of banks is described with reference to FIG. 37. FIG. 37 is a circuit diagram of a background art circuit architecture for controlling different banks independently. The use of the banks is advantageous in that the RAM is efficiently utilized by independent control for each bank.
A device receives a row-address and a bank-address. Row bank selectors select the row-address in accordance with the bank-address to hold and output the selected row-address as a local row-address. As a result, only the local row-address selected depending upon the bank-address is activated, and the row decoder RD corresponding to the selected local row-address (for example, the row decoder of the bank BANK100) is activated. The row decoder RD selects a main word line MWL to hold the state wherein the main word line MWL is selected.
The function of the plurality of row bank selectors to independently hold the local row-addresses permits independent control of the plurality of banks. Specifically, a circuit operation to be described below may be performed. First, the bank-address selects the bank BANK100 and the row-address activates one main word line MWL. Then, the bank-address and the row-address are successively provided in this state to activate the main word line of a bank BANK110. Since the row bank selectors independently hold the row-addresses, the successively provided local row-addresses may differ from each other.
After the selection of the main word line, a column-address and the bank-address are applied to the device. Column bank selectors select the column-address in accordance with the bank-address to output the selected column-address as a local column-address. As a result, only the local column-address selected depending upon the bank-address is activated, and the column decoder CD of, for example, the bank BANK100 is accordingly activated to select a column selection line CSL.
The above described architecture is subjected to various restrictions in dividing one memory array into the plurality of banks to efficiently use the RAM. The restrictions are described hereinafter on the assumption that the bank BANK100 is divided by the dotted line of FIG. 37 into two new banks arranged in the column direction.
The activation of the main word line and retention of this state must be performed independently for each of the banks resulting from the division. It is hence necessary to provide a row decoder for holding the local row-address in each of the banks resulting from the division. The provision of the row decoder in each of the banks adds to the circuit area.
The bank division presents a problem in association with the amplification of data of memory cells included in the RAM. As illustrated in FIG. 36, data read from a memory cell MC onto data lines DL are amplified by a pair of sense amplifier groups SAG disposed in the column direction on opposite sides of a sub-array containing the memory cell MC. More specifically, each of the sense amplifier groups SAG comprises a plurality of sense amplifiers SA for amplifying data. Both of the pair of sense amplifier groups SAG on opposite sides of one sub-array are involved in the amplification of the data in the sub-array. The amplified data are held in the sense amplifiers SA.
When the bank BANK100 is divided by the dotted line of FIG. 36, two sub-arrays on opposite sides of each sense amplifier group SAG lying in a boundary part of the divided banks can be activated simultaneously. For example, it is assumed that both main word lines MWL1 and MWL2 are activated. Based on the above described data amplification mechanism, the sense amplifier groups SAG on opposite sides of the sub-arrays in which the main word lines MWL1 and MWL2 are present are to be involved in the amplification. Then, each sense amplifier group SAG in the boundary part must simultaneously amplify the data of two sub-arrays to sacrifice the data of one of the sub-arrays.
To solve the above described problem, an architecture has been used wherein the sense amplifier groups SAG are doubled in the boundary part. FIG. 38 is a circuit diagram of a RAM which comprises row decoders RD100, RD101, and sense amplifier groups SAG arranged so that some of the sense amplifier groups SAG which lie in the boundary part are provided pairwise.
The row decoders RD100 and RD101 are provided in corresponding relation to two banks BANK100 and BANK101 formed by dividing the bank BANK100 of FIG. 36. The row bank selectors of FIG. 37 (not shown in FIG. 38) are provided for independently controlling the row decoders RD100 and RD101. The row bank selectors independently apply the local row-addresses to the row decoders RD100 and RD101. The sense amplifier groups SAG provided pairwise in the boundary part permit the individual data amplification in the banks BANK100 and BANK101.
Such an architecture allows independent selection and retention of main word lines MWL0 and MWL1 having different row-addresses in each of the banks into which one memory array is divided.
The pairwise formation of the sense amplifiers SAG in the boundary part, however, increases the number of sense amplifier groups SAG as the number of banks into which the memory array is divided increases, resulting in the increase in the layout area of the memory array.